This invention relates to a semiconductor device, and more particularly to a semiconductor memory device having a Bi-CMOS structure of the composite type which comprises bipolar and CMOS transistors.
Devices of Bi-CMOS structures made up by the combination of bipolar and CMOS transistors combine the high speed property of the bipolar transistor and the high density property of the CMOS transistor, thus making it possible to realize a high density and high speed semiconductor memory device.
A conventional semiconductor memory device of the Bi-CMOS structure is shown in FIG. 1. Each memory cell 1 comprises CMOS transistors in accordance with the high density requirement. For example, a memory cell of the six-transistor type comprised of six MOS transistors or a memory cell comprising a high resistance polysilicon as the load of the MOS transistors is employed. To a pair of bit lines 3 and 4 connected to the memory cell 1, NMOS transistors 2 as a load are connected, respectively. To the memory cell 1, a word line 5a is connected. Transfer gates 5 which are paired with each other and controlled by a column select line 6 are provided on the paired bit lines 3 and 4, respectively. Further, sense lines 7 and 8 are connected to the bit lines 3 and 4, respectively. These sense lines 7 and 8 are connected to a sense amplifier 9. The sense amplifier 9 comprises a pair of bipolar transistors 9a for which the emitters are commonly connected, a pair of resistance loads 9b connected in series therewith, and a constant current source 9c connected to the common junction of the emitters of the pair of bipolar transistors 9a.
When the word line 5a is raised to a high potential for selection, the bit line 21 connected to the side where the driver transistor of the memory cell 1 is on, draws a current thereinto, so that the potential thereof takes a value lower than that of the bit line connected to the side where the driver transistor of the memory cell 1 is off. The difference between the potentials on the bit lines 3 and 4 passes through the transfer gates 5 opened by the column select line 6 and is output to the sense lines 7 and 8. The difference between the potentials on the sense lines 7 and 8 is amplified by the sense amplifier 9. The amplified output is outputted from the collector of the bipolar transistor 9a.
Since the conventional semiconductor memory device constituted as above uses a high sensitivity sense amplifier comprising bipolar transistors, it is possible to suppress the potential difference .DELTA.V across bit lines so that it is equal to a small value. On the other hand, the delay time .DELTA.t is expressed by the following equation: EQU Delay time.DELTA.t=C.multidot..DELTA.V/i (1),
where C is a capacitance value of a bit line and i is a current value flowing to a selected cell. Since the voltage difference .DELTA.V across the bit lines is small, high speed access can be realized.
With the conventional semiconductor memory device, however, the following problems occur because of descaling of the memory cells resulting from the requirement of high memory capacity and/or an increase in parasitic capacitance connected to bit lines and sense lines. The parasitic capacitance of the bit lines 3 and 4 is due to the drain of an MOS transistor of a non-selected memory cell 1 and/or the wiring, and the parasitic capacitance of the sense lines 7 and 8 is due to the drain of the transfer gate 5 of non-selected bit line 3 or 4. Especially, when the parasitic capacitance by the drain of the transfer gate 5 is large, it is required to draw a large quantity of current from the bit lines 3 and 4 at the time of writing into the memory cell 1, resulting in the problem that the size of the transistor cannot be reduced.
Further, by the back-gate effect of the transfer gate 5, the conductance becomes high with respect to the potential on the side of high potential of the bit lines 3 and 4, so that a voltage is difficult to reach the sense amplifier 9. Since it is necessary to supply a base current to the sense amplifier 9, it is necessarily required for high speed operation to maintain the high potential side at a low impedance. Accordingly, the conventional semiconductor device has the problem that it is difficult to perform high speed operation.
A further problem lies in that the drawing current of the memory cell 1 bearing the current value i in the above-mentioned equation (1) cannot be set to a large value, when the narrow channel effect is taken into account, because the size of the transistor on the drive side of the memory cell must be reduced because of high density requirement.
Thus, with the conventional semiconductor memory device, for the potentials on the sense lines 7 and 8, as shown in FIG. 2, the potential on the side of the high potential thereof cannot exceed above a reference potential 10, so that the potential difference across the sense lines 7 and 8 can only take a value of about 0.5 volts. In addition, with the conventional semiconductor memory device, a large parasitic capacitor is charged and discharged by a small current, and the conductance of the bit line on the side of high potential is high when viewed from the side of the sense amplifier, so that the performance of the sense amplifier comprised of bipolar transistors in not sufficiently exhibited.